1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a technique effective in driving for inverting a polarity of video signals to be applied to pixels every two rows.
2. Description of the Related Art(s)
The liquid crystal display device includes a liquid crystal display panel having a liquid crystal material sealed between two substrates, and a driver circuit that drives the liquid crystal display panel. In a display region of the liquid crystal display panel, pixels each having a pixel electrode and a common electrode are arranged in a matrix having a horizontal direction as a row direction, and a vertical direction as a column direction. The pixel electrode in each of the pixels is set to a voltage corresponding to display data, and each of the pixel expresses a gradation according to an orientation of liquid crystal molecules which are controlled by a potential difference between the pixel electrode and the common electrode.
The liquid crystal display panel of an active matrix system includes scanning signal lines disposed for respective pixel rows, video signal lines disposed for respective pixel columns, and active elements for the respective pixels. The active elements are, for example, thin film transistors (TFTs), and each of the TFTs has a gate connected to one of the scanning signal lines, a drain connected to one of the video signal lines, and a source connected to one of pixel electrodes.
The liquid crystal display panel is early deteriorated if the liquid crystal display panel is driven by a DC current. In order to suppress the deterioration, an AC voltage driving that periodically inverses a polarity of a voltage between the pixel electrode and the common electrode is conducted. The polarity is set to be positive if a potential of a gradation voltage (video signal) to be applied to the pixel electrode is higher than a potential of a common voltage to be applied to the common electrode, and set to be negative if the potential of the gradation voltage is lower than the potential of the common potential.
As the AC voltage driving, there are a row line inversion driving system and a dot inversion driving system. In the row line inversion driving system, a plurality of pixel rows configuring an image of one frame is set to be alternately positive and negative, and in the dot inversion driving system, the plurality of pixels arranged in a matrix is set to be alternately positive and negative in each of the row direction and the column direction. In the AC voltage driving, for example, the video signal lines are charged or discharged with the inversion of the polarity to increase a power consumption. The power consumption associated with the charge and discharge operation basically becomes larger as a drive voltage is larger, and also as an inversion frequency is higher. For that reason, in the display device having the liquid crystal display panel of a high resolution, the inversion frequency is lowered as N-line (row) inversion driving that inverts the polarity every N rows (N≧2), and the power consumption can be reduced.
FIG. 8 is a block diagram of a display control circuit that controls the drive of the liquid crystal display panel. A display control circuit (ICON) 2 receives display data DATA, a display timing signal DTMG, and a dot clock signal DCLK from an image signal source outside the liquid crystal display device. A driver control signal generation block 4 within the display control circuit 2 controls the drive of the liquid crystal display panel on the basis of those input signals. A drain driver (video signal line driver circuit) receives display data DATA_A, a reference clock CL2, a start pulse STH, a data latch pulse CL1, and an AC signal M among the signals output from the driver control signal generation block 4. A gate driver (scanning signal line driver circuit) receives a gate start pulse FLM and a gate shift clock CL3.
FIG. 9 is a timing chart of input/output signals of the display control circuit 2, and potentials of drain signal lines (video signal lines) and gate signal lines (scanning signal lines). In FIG. 9, DCLK and CL2 are omitted. DTMG denotes a data enable signal, and indicates a valid period (active period) of the display data input. DTMG is H (high) level in the active period, and in this example, a width of the active period provided for each horizontal scanning period (1H) is represented by τDE. DATA_T is identical with DATA from the external, and DATA input by serial transmission in synchronization with DCLK from the external during the active period is written into a latch circuit of the drain driver in synchronization with CL2. CL2 has the same frequency as that of DCLK, and a write period of display data for one row into the latch circuit is τDE. CL1 is generated in synchronization with a timing of write completion into the latch circuit in the 1H period, and the drain driver converts the display data for one row, which is held in the latch circuit, into a video signal in synchronization with CL1, and supplies the video signal to a group of drain signal lines. FIG. 9 illustrates two-line inversion driving, and converts video signals on a (2n−1) row and a 2n row (n is a natural number) into video signals having the same polarity. The video signal on each row is supplied to each drain signal line every 1H period, and a TFT of a corresponding row turns on by a gate pulse (scanning signal) which is applied to the gate signal line, to write the video signal into the pixel electrode.